SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 324

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chip Select/Wait Controller (2 of 4)
Mnemonic Name Address
BMA2
BMA3
Address
Register
Address
Register
Base/
Base/
Mask
Mask
E40CH
E408H
FFFF
FFFF
Bits 8–0 specify the address bits (A23–A15) to be masked
0: The corresponding address bit is not masked.
1: The corresponding address bit is masked.
Must be
written as
0.
Bits 8–0 specify the address bits (A23–A15) to be masked
0: The corresponding address bit is not masked.
1: The corresponding address bit is masked.
Must be
written as
0.
15
23
31
15
23
31
7
7
1
0
0
0
1
0
0
0
Must be
written as
0.
Must be
written as
0.
TMP1940CYAF-282
14
22
30
14
22
30
6
6
1
0
0
0
1
0
0
0
Must be
written as
0.
Must be
written as
0.
13
21
29
13
21
29
5
5
1
0
0
0
1
0
0
0
A23–A16 of the starting address for CS2
A31–A24 of the starting address for CS2
A23–A16 of the starting address for CS3
A31–A24 of the starting address for CS3
Must be
written as
0.
Must be
written as
0.
12
20
28
12
20
28
4
4
1
0
0
0
1
0
0
0
MA2
R/W
MA2
R/W
R/W
R/W
MA3
R/W
MA3
R/W
R/W
R/W
BA2
BA2
BA3
BA3
Must be
written as
0.
Must be
written as
0.
19
27
19
27
11
11
3
3
1
0
0
0
1
0
0
0
Must be
written as
0.
Must be
written as
0.
TMP1940CYAF
10
18
26
10
18
26
2
2
1
0
0
0
1
0
0
0
Must be
written as
0.
Must be
written as
0.
17
25
17
25
1
9
1
9
1
0
0
0
1
0
0
0
Address
mask
0: Not
1: Masked
Address
mask
0: Not
1: Masked
masked
masked
16
24
16
24
0
8
0
8
1
0
0
0
1
0
0
0