SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 410

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.3
CPU-to-Flash Interface
programming modes. The diagram does not show the actual logic network; instead it is only a
conceptual depiction of the CPU-to-flash interface.
Figure 3.17 illustrates the internal interface between the CPU and the flash memory in on-board
CPU
CPU
Figure 3.16 Flash Memory Block Architecture
A31 – A17
Figure 3.17 Internal CPU-to-Flash Interface
D31 – D0
A16 – A2
0xxxx7_FFFF
RESET
x: Depends on the TMP1940FDBF operation mode
WR
RD
Operation
Mode
Single-Chip mode: 0x1FC0_0000 – 0x1FC7_FFFF (physical address)
Single Boot mode: 0x4000_0000 – 0x4007_FFFF (physical address)
TMP1940FDBF-52
Decoder
Register
32 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
8 Kbytes
4 Kbytes
4 Kbytes
CE
DQ31 – DQ0
RDY_BSY
AD14 – AD0
WE
RESET
OE
Flash Memory
(512 KB)
TMP1940FDBF