SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 177

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12. 16-Bit Timer/Event Counters (TMRBs)
External Pins
Registers
(Addresses)
TMRB3). Each channel has the following three basic operating modes:
double-buffered), two 16-bit capture registers, two comparators, capture control logic, a timer flip-flop and its
associated control logic.
external clock/capture trigger inputs. Table 12.1 gives the pins and registers for the four channels. In the
following sections, any references to the TMRB0 also apply to all the other channels.
The TMP1940CYAF has a 16-bit timer/event counter consisting of four identical channels (TMRB0–
Each channel has the capture capability used to latch the value of the counter. The capture capability allows:
Figure 12.1 to Figure 12.4 are block diagrams of the TMRB0 to TMRB3.
The main components of a TMRBn block are a 16-bit up-counter, two 16-bit timer registers (one of which is
Each channel is independently programmable and functionally equivalent except that the TMRB3 has no
16-bit interval timer mode
16-bit event counter mode
16-bit programmable pulse generation (PPG) mode
Frequency measurement
Pulse-width measurement
Time difference measurement
External clock /
Capture trigger
inputs
Timer flip-flop output
Timer Run register
Timer Mode register
Timer Flip-Flop
Control register
Timer registers
Capture registers
Table 12.1 Pins and Registers for the Four TMRBn Channels
TB0IN0
(Shared with P74)
TB0IN1
(Shared with P75)
TB0OUT0
(Shared with P76)
TB0RUN
(0xFFFF_F180)
TB0MOD
(0xFFFF_F182)
TB0FFCR
(0xFFFF_F183)
TB0RG0L
(0xFFFF_F188)
TB0RG0H
(0xFFFF_F189)
TB0RG1L
(0xFFFF_F18A)
TB0RG1H
(0xFFFF_F18B)
TB0CP0L
(0xFFFF_F18C)
TB0CP0H
(0xFFFF_F18D)
TB0CP1L
(0xFFFF_F18E)
TB0CP1H
(0xFFFF_F18F)
TMRB0
TMP1940CYAF-135
TB1IN0
(Shared with P80)
TB1IN1
(Shared with P81)
TB1OUT0
(Shared with P82)
TB1RUN
(0xFFFF_F190)
TB1MOD
(0xFFFF_F192)
TB1FFCR
(0xFFFF_F193)
TB1RG0L
(0xFFFF_F198)
TB1RG0H
(0xFFFF_F199)
TB1RG1L
(0xFFFF_F19A)
TB1RG1H
(0xFFFF_F19B)
TB1CP0L
(0xFFFF_F19C)
TB1CP0H
(0xFFFF_F19D)
TB1CP1L
(0xFFFF_F19E)
TB1CP1H
(0xFFFF_F19F)
TMRB1
TB2IN0
(Shared with P83)
TB2IN1
(Shared with P84)
TB2OUT
(Shared with P85)
TB2RUN
(0xFFFF_F1A0)
TB2MOD
(0xFFFF_F1A2)
TB2FFCR
(0xFFFF_F1A3)
TB2RG0L
(0xFFFF_F1A8)
TB2RG0H
(0xFFFF_F1A9)
TB2RG1L
(0xFFFF_F1AA)
TB2RG1H
(0xFFFF_F1AB)
TB2CP0L
(0xFFFF_F1AC)
TB2CP0H
(0xFFFF_F1AD)
TB2CP1L
(0xFFFF_F1AE)
TB2CP1H
(0xFFFF_F1AF)
TMRB2
TMP1940CYAF
TB3OUT
(Shared with P86)
TB3RUN
(0xFFFF_F1B0)
TB3MOD
(0xFFFF_F1B2H
TB3FFCR
(0xFFFF_F1B3)
TB3RG0L
(0xFFFF_F1B8)
TB3RG0H
(0xFFFF_F1B9)
TB3RG1L
(0xFFFF_F1BA)
TB3RG1H
(0xFFFF_F1BB)
TB3CP0L
(0xFFFF_F1BC)
TB3CP0H
(0xFFFF_F1BD)
TB3CPIL
(0xFFFF_FIBE)
TB3CPIH
(0xFFFF_FIBF)
TMRB3