SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 66

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6.4
Wake-up Signaling
up signaling depends on the settings of the Interrupt Mask Level bits, CMask[15:13], of the CP0 Status
register and the current standby mode (see Table 5.7).
There are two ways to exit a standby mode: an interrupt request or reset signal. Availability of wake-
Wake-up via Interrupt Signaling
Wake-up via Reset Signaling
The operation upon return from a standby mode varies, depending on the interrupt priority level
programmed before entering a standby mode. If the interrupt priority level is greater than the
processor’s interrupt mask level, execution resumes with the interrupt service routine. Upon
completion of the interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated the standby mode (i.e., the instruction that set
the Halt or Doze bit in the Config register).
If the interrupt priority level is equal to or less than the processor’s interrupt mask level, program
execution resumes with the instruction that activated the standby mode. The interrupt is left
pending.
Nonmaskable interrupts are always serviced upon return from a standby mode, regardless of the
current interrupt mask level.
Reset signaling always brings the TMP1940CYAF out of any standby mode. A wake-up from
STOP mode must allow sufficient time for the oscillator to restart and stabilize (see Table 5.1).
A reset does not affect the contents of the on-chip RAM, but initializes everything else, whereas an
interrupt preserves all internal states that were in effect before the standby mode was entered.
TMP1940CYAF-24
TMP1940CYAF