SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 367
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
SW00ENB-ZCC
Manufacturer Part Number
SW00ENB-ZCC
Description
MCU, MPU & DSP Development Tools CASEWORKS
Manufacturer
Toshiba
Datasheet
1.SW00ENB-ZCC.pdf
(464 pages)
Specifications of SW00ENB-ZCC
Tool Type
Development Software Support
Core Architecture
870
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 367 of 464
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DSU Debug Interface
If the DSU pin is sampled low at the rising edge of RESET , the Port A pins are configured as interface signals for an
external real-time debug system. The DSU pin has an internal pullup resistor.
(PA7)
DCLK
(PA0)
(PA5)
PCST[2]
(PA1)
PCST[1]
(PA2)
PCST[0]
(PA3)
SDI/ DINT
(PA6)
SDAO/TPC
(PA4)
DRESET
DBGE
The following shows the DSU interface signals.
O
O
O
O
O
I
I
I
Debug Reset
Debug Clock
DCLK signal for an external real-time debug system
Debugger Enable
PC Trace Status [2]
PCTS[2] signal for an external real-time debug system
PC Trace Status [1]
PCST[1] signal for an external real-time debug system
PC Trace Status [0]
PCTS[0] signal for an external real-time debug system
Serial Data Input / Debug Interrupt
SDI/ DINT signal for an external real-time debug system
Serial Data and Address Output / Target PC
SDAO/TPC signal for an external real-time debug system
DRESET signal for an external real-time debug system
DBGE signal for an external real-time debug system
Figure 2.2 DSU Interface Signals
TMP1940FDBF-9
TMP1940FDBF
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