SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 436

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.7.14
3.7.15
3.7.16
terminates the block protect operation. The Block Protect command that was interrupted should be re-
initiated once the flash memory is ready to accept another command sequence (see Figure 3.31).
command must be written to verify the protect status after executing Block Protect. If the desired block
is not in the protected state, the Block Protect command sequence must be re-initiated.
Block Unprotect Command
before executing the Block Unprotect command. After the Block Unprotect command sequence is
complete, block uprotection is performed by pulsing
immediately terminates the block unprotect operation. The Block Unprotect command that was
interrupted should be re-initiated from protecting all blocks. The Verify Block Protect command must
be written to verify the protect status after executing Block Unprotect.
Verify Block Protect Command
is a four-bus-cycle operation. The address of the block to be verified is given in the fourth cycle. Any
address within the block range will suffice, provided A0 = 1 and A5 = 0. Data must be read as a 16-bit
halfword. If the selected block is protected, a value of 0x0001 is returned. If the selected block is not
protected, a value of 0x0000 is returned. Following the fourth bus cycle, an additional block address
may be provided.
Read/Reset command or a hardware reset is required to reset the flash memory to Read mode or to write
the next command.
Write Operation Status
embedded operation: DQ7, DQ5, DQ3 and RDY_BSY. These status bits can be read during an
embedded operation using the same timing as for Read mode by setting
RDY_BSY status is valid after the rising edge of the final
WE
Program command on a protected block
Erase command on a protected block
Chip Erase command when all the blocks are
protected
Chip Erase command when any blocks are protected
Multi-Block Erase command when any blocks are
protected
Any commands written during the Block Protect algorithm are ignored. A hardware reset immediately
Note that the block protect operation is not verified automatically. The Verify Block Protect
Any commands written during the Block Unprotect algorithm are ignored. A hardware reset
After the command sequence is complete, writing to the protect control logic is performed by pulsing
The Block Unprotect command unprotects all blocks simultaneously. All blocks must be protected
The Verify Block Protect command is used to verify the protect status of a block. Verify Block Protect
The Verify Block Protect command does not return the flash memory to Read mode. Either the
As shown in Table 3.28, the flash memory provides several flag bits to determine the status of an
for t
Table 3.23 Effects of the Program and Erase Commands on the Protected Blocks
PPLH
while
Command
CE
is set to V
TMP1940FDBF-78
IL
and the block address is placed on P70 (A16) to P54 (A12).
No programming operation is performed, and the flash
memory automatically returns to Read mode.
No erase operation is performed, and the flash memory
automatically returns to Read mode.
No erase operation is performed, and the flash memory
automatically returns to Read mode.
Only the unprotected blocks are erased. Upon completion,
the flash memory automatically returns to Read mode.
Only the unprotected blocks are erased. Upon completion,
the flash memory automatically returns to Read mode.
WE
for t
PULH
WE
with
pulse in the command sequence,
Operation
TMP1940FDBF
CE
set to V
CE
and
IL
OE
.
to V
IL
. The