SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 284

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3 Operation
TMP1940CYAF allows the user to program the time-out period in the WDTP[1:0] field in the WDMOD.
While enabled, the software can reset the counter to zero at any time by writing a special clear-count code. If
the software is unable to reset the counter before it reaches the time-out count, the WDT generates the
INTWDT interrupt. In response to the interrupt, the CPU jumps to a system recovery routine to regain
control of the system.
automatically and stops counting. The WDT continues counting while an off-chip peripheral has mastership
of the bus (i.e., BUSAK = 0).
I2WDT bit can be programmed before putting the TMP1940CYAF in IDLE mode.
The watchdog timer is a kind of timer that generates an interrupt request if it times out. The WDT of the
The WDT begins counting immediately after reset.
When the TMP1940CYAF goes into SLEEP or STOP mode, the WDT counter is reset to zero
In IDLE mode, the I2WDT bit in the WDMOD determines whether or not to disable the WDT. The
Examples:
Clearing the WDT binary counter
Programming the time-out interval to 2
Disabling the watchdog timer
WDCR
WDMOD
WDMOD
WDCR
7 6 5 4 3 2 1 0
0 1 0 0 1 1 1 0
7 6 5 4 3 2 1 0
1 0 1
7 6 5 4 3 2 1 0
0
1 0 1 1 0 0 0 1
TMP1940CYAF-242
18
Writes the clear-count code (4EH) to the WDCR.
Clears the WDTE bit to 0.
Writes the disable code (B1H) to the WDCR.
/fsys
TMP1940CYAF