SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 415

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

and A1 = 0) to read valid status information. During the embedded erase operation, the system must
provide an address (with A0 = 0 and A1 = 0) within any of the blocks selected for erasure to read valid
status information.
During the embedded program operation, the system must provide the program address (with A0 = 0
DQ7 (Data Polling)
The Data Polling bit, DQ7, indicates to the host system the status of the embedded operation.
Data Polling is valid after the final bus write cycle of an embedded command sequence.
When the embedded Program algorithm is in progress, an attempt to read the flash memory will
produce the complement of the data last written to DQ7. Upon completion of the embedded
Program algorithm, an attempt to read the flash memory will produce the true data last written
to DQ7. Therefore, the system can use DQ7 to determine whether the embedded Program
algorithm is in progress or complete.
When the embedded Erase algorithm is in progress, an attempt to read the flash memory will
produce a 0 at the DQ7 output. Upon completion of the embedded Erase algorithm, the flash
memory will produce a 1 at the DQ7 output.
If there is a failure during an embedded operation, DQ7 continues to output the same value.
Thus, DQ7 must always be polled in conjunction with the Exceeded Timing Limits (DQ5) flag.
Figure 3.21 shows the DQ7 polling algorithm.
The flash memory disables address latching when an embedded operation is complete. Data
polling must be performed with a valid programmed address or an address within any of the
non-protected blocks selected for erasure.
DQ5 (Exceeded Timing Limits)
DQ5 produces a 0 while the program or erase operation is in progress normally. DQ5 produces
a 1 to indicate that the program or erase time has exceeded the specified internal limit. This is a
failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition also appears if the system tries to program a 1 to a location that was
previously programmed to a 0. Only an erase operation can change a 0 back to a 1. In this case,
the embedded Program algorithm halts the operation. Once the operation has exceeded the
timing limits, DQ5 will indicate a 1. Note that this is not a device failure condition since the
flash memory was used incorrectly.
Under both these conditions, the flash memory remains locked in Embedded Operation mode.
The system must issue the Read/Reset command to return the flash memory to Read mode.
DQ3 (Block Erase Timer)
After the completion of the sixth bus cycle of the Auto Block Erase command sequence, the
block erase time-out window of 50 m begins. The erase operation will begin after the time-out
has expired. When the time-out is complete and the erase operation has begun, DQ3 switches
from 0 to 1. If DQ3 is 0, the flash memory will accept additional Auto Block Erase commands.
Each time an Auto Block Erase command is written, the time-out window is reset. To ensure
that the command has been accepted, the system should check DQ3 prior to and following each
Auto Block Erase command. If DQ3 is 1 on the second status check, the command might not
have been accepted.
TMP1940FDBF-57
TMP1940FDBF