SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 186

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2.6
12.2.7
Comparators (CP0 and CP1)
(UC0) with a time constant value in the TB0RG0. The CP1 block compares the output of the UC0 with
a time constant value in the TB0RG1. When a match is detected, an interrupt (INTTB00/INTTB01) is
generated.
Timer Flip-Flop (TB0FF0)
the comparators and latch signals from the capture control logic. The toggling of the TB0FF0 can be
enabled and disabled through the programming of the TB0C1T1, TB0C0T1, TB0E1T1 and TB0E0T1
bits in the TB0FFCR register.
writing 01 or 10 to the TB0FF0C[1:0] field in the TB0FFCR. A write of 01 to this field sets the
TB0FF0; a write of 10 to this field clears the TB0FF0. Additionally, a write of 00 causes the TB0FF0 to
be toggled to the opposite value.
Port 7 registers (P7CR and P7FC) must be programmed to configure the P76/TB0OUT pin as TB0OUT.
Note: Programming the TB0FF0C[1:0] field should only be attempted when the timer is not running.
The TMRB0 contains two 16-bit comparators. The CP0 block compares the output of the up-counter
The timer flip-flop (TB0FF0) is toggled, if so enabled, upon assertion of match-detect signals from
Upon reset, the TB0FF0 assumes an undefined state. The TB0FF0 can be initialized to 1 or 0 by
The value of the TB0FF0 can be driven onto the TB0OUT pin, which is multiplxed with P76. The
TMP1940CYAF-144
TMP1940CYAF