SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 417

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TMP1940FDBF
Securing the flash (Disabling read accesses)
Securing the flash memory disables a general-purpose programmer to read its contents. To turn
on the security feature, once programming is complete, set the FSE bit in the FLCS register and
write the Auto Security On command. After the completion of the fourth bus cycle of that
command sequence, the embedded Security On algorithm automatically programs and verifies
the security bit.
Any commands written during the embedded operation are ignored. A hardware reset
immediately terminates the embedded operation. The FSE bit must not be altered throughout
the embedded operation.
When the embedded algorithm completes, the flash memory automatically returns to Read
mode. In on-board operating modes, the CPU can read the flash memory even if the security is
on; clear the FSE bit to 0 to enable access to the flash array.
If any failure occurs during the embedded operation, the flash memory remains locked in
Embedded Operation mode and does not return to Read mode. The system can determine the
status of the embedded operation by using write status flags. Note that this is a security bit
failure. If the flash memory needs to be secured, the chip should be replaced. When the security
is on, any reads by programming equipment will always return a halfword-length value of
0x0098.
Unsecuring the flash (Enabling read accesses)
The security feature is designed to disable reads of the flash memory by programming
equipment. While the TMP1940FDBF is soldered on a board, the CPU can always read the
flash memory, regardless of whether or not the security is on. Since the flash memory is placed
under control of a user’s application program in on-board operating modes, it is not easy for
third parties to perform intrusive access to the flash memory. Therefore, within the confines of
a board, the flash memory does not need to be secured.
To turn off the security feature, set the FSE bit in the FLCS register and write the Auto Security
Off command. After the completion of the sixth bus cycle of that command sequence, the
embedded Security Off algorithm automatically erases and verifies the entire flash array, and
then erases and verifies the security bit.
Any commands written during the embedded operation are ignored. A hardware reset
immediately terminates the embedded operation. In this case, if any erase operation is in
progress, data may be corrupted. The FSE bit must not be altered throughout the embedded
operation.
When an embedded algorithm completes, the flash memory automatically returns to Read
mode. If any on-board operation is subsequently required, clear the FSE bit to 0 to enable
access to the flash array.
If any failure occurs during an embedded operation, the flash memory remains locked in
Embedded Operation mode and does not return to Read mode. The system can determine the
status of the embedded operation by using write status flags. If a failure occurs in the memory
array, the security bit is not erased. In this case, the security is left on. The chip should be
replaced if a memory array or security bit failure occurs.
The Auto Security Off command erases the flash array prior to turning off the security feature.
Even if a given block is protected, it is unconditionally erased, but the protect status of that
block remains unchanged. The Auto Security Off and Auto Chip Erase command sequences are
the same. The only difference is that the Auto Security Off command requires the FSE bit to be
TMP1940FDBF-59