SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 399

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.9
Show Flash Memory Sum Command
(12) The 27th to mth bytes from the controller are stored in the on-chip RAM of the TMP1940FDBF.
(13) The (m+1)th byte is a checksum value. To calculate the checksum value, add the 27th to mth bytes
(14) The (m+2)th byte is a acknowledge response to the 27th to (m+1)th bytes.
(15) If the (m+2)th byte was a normal acknowledge response, a branch is made to the address specified
(1) The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command.
(2) The 3rd byte, which the target board receives from the controller, is a command. The code for the
(3) The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the
See Table 3.7.
Storage begins at the address specified by the 19th–22nd bytes and continues for the number of
bytes specified by the 23rd–24th bytes.
together, drop the carries and take the two’s complement of the total sum. Transmit this checksum
value from the controller to the target board. The checksum calculation is described in details in
Section 3.5.15.
First, the RAM Transfer routine checks for a receive error in the 27th to (m+1)th bytes. If there
was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it
waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge
response are the same as those of the previously issued command (i.e., all 1s). When the SIO0 is
configured for I/O Interface mode, the RAM Transfer routine does not check for a receive error.
Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding
the series of the 27th to (m+1)th bytes must result in zero (with the carry dropped). If it is not
zero, one or more bytes of data has been corrupted. In case of a checksum error, the RAM Transfer
routine sends back 11H to the controller and returns to the state in which it waits for a command
(i.e., the 3rd byte) again.
by the 19th to 22nd bytes in 32-bit ISA mode.
Show Flash Memory Sum command is 20H.
3rd byte. Before sending back the acknowledge response, the boot program checks for a receive
error. If there was a receive error, the boot program transmits x8H and returns to the state in which
it waits for a command again. In this case, the upper four bits of the acknowledge response are
undefined — they hold the same values as the upper four bits of the previously issued command.
When the SIO0 is configured for I/O Interface mode, the boot program does not check for a
receive error.
If the 3rd byte is equal to any of the command codes listed in Table 3.5 on page 33, the boot
program echoes it back to the controller. When the Show Flash Memory Sum command was
Note: At this point, r29 (sp) points to address 0xFFFF_9100. Program control must not be transferred
When the above checks have been successful, the RAM Transfer routine returns a normal
acknowledge response (10H) to the controller.
The RAM storage start address must be within the range 0xFFFF_8000–0xFFFF_8FFF.
from the RAM back to the boot ROM.
TMP1940FDBF-41
TMP1940FDBF