SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 283

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WDMOD
(0xFFFF_F090)
WDCR
(0xFFFF_F091)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Time-out peiord (@ fc
System Clock Select
SYSCR1.SYSCK
Figure 16.4 Watchdog Timer Mode Register (WDMOD)
Figure 16.5 Watchdog Timer Control Register (WDCR)
0 (fgear)
1 (fs)
WDT
enable
1: Enable
B1H: WDT disable code
4EH : WDT clear-count code
WDTE
R/W
7
7
1
Time-out period
00: 2
01: 2
10: 2
11: 2
32 MHz, fs
WDTP1
SYSCR1.GEAR[1:0]
6
6
0
Clock Gear Value
16
18
20
22
TMP1940CYAF-241
/fsys
/ fsys
/ fsys
/ fsys
R/W
01 (fc/
10 (fc/
11 (fc/
00 (fc)
xxx
WDTP0
32.768 kHz)
2
4
8
)
)
)
5
5
0
16.384 ms
2.0 s
2.048 ms
4.096 ms
8.192 ms
4
4
00
Special code
W
System reset
WDT enable
Other values
Watchdog Timer Time-out Period
0
1
0
1
B1H
4EH
16.384 ms
32.768 ms 131.072 ms
65.536 ms 262.144 ms 1048.576 ms
8.0 s
8.192 ms
3
3
WDMOD.WDTP[1:0]
Disable
Enable
Internally routes the WDT time-out signal
to the system reset
01
IDLE
0: Off
1: On
TMP1940CYAF
I2WDT
WDT disable code
WDT clear-count code
Don’t care
32.768 ms
65.536 ms
2
32.0 s
2
0
10
R/W
1: System
RESCR
reset
1
1
0
128.0 s
131.072 ms
262.144 ms
524.288 ms
11
Must be
written as
0.
R/W
0
0
0