SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 267

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SIOS Bit
SIOF Bit
SEF Bit
SCK Output
SI Pin
IINTS2 Interrupt
Request
SBI0DBR
(3) 8-Bit Transmit/Receive Mode
SBI0DBR. Then setting the SIOS bit in the SBI0CR1 initiates transmission and reception. The
transmit data is shifted out through the SO pin, with the least-significant bit (LSB) first, with the
falling edge of the serial clock, while at the same time the receive data is shifted in through the SI
pin with the rising edge of the serial clock. Once the shift register is fully loaded with eight bits of
the received data, it is transferred to the SBI0DBR, and the INTS2 interrupt is generated. The
INTS2 interrupt service routine must then pick up the received data from the SBI0DBR and writes
the next transmit data into the SBI0DBR. Because the SBI0DBR is shared between transmit and
receive operations, the received data must be read before the next transmit data is written.
received data until a write of the transmit data.
software must read the received data and write the transmit data before the next shift operation
begins. In this mode, the maximum data rate is a function of the maximum latency between when
the INTS2 interrupt is generated and when the interrupt service routine reads the received data and
writes the transmit data.
appears on the SO pin between when the SBI0SR.SIOF bit is set and when SCK subsequently goes
low.
SIOS bit to 0 or setting the SIOINH bit to 1. If the SIOS bit is cleared, reception continues until the
shift register is fully loaded and transferred to the SBI0DBR. In this case, software can check the
SBI0SR.SIOF bit to determine whether transmission/reception has come to an end (0 = end-of-
reception/transmission). If the SIOINH bit is set, the ongoing transmission/reception is aborted
immediately, and the SIOF bit is cleared at that point.
Note:
Configure the SIO interface in transmit/receive mode and write the transmit data into the
In internal clock mode, the SIO interface will be in wait state (SCK will stop) after a read of the
In external clock mode, shift operations continue, synchronous to the external clock. Therefore,
At the beginning of a transmission, the value of the last bit of the previously transmitted byte
Transmission/reception can be terminated by the INTS2 interrupt service routine clearing the
The contents of the SBI0DBR is not preserved after changing the transfer mode. Before
changing
transmission/reception and have the INTS2 interrupt service routine pick up the last
received data.
Figure 14.26 Receive Mode (Internal Clock Mode)
a
0
the
a
1
transfer
TMP1940CYAF-225
a
2
a
3
mode,
a
4
a
5
clear
Read of the received data
a
6
the
a
7
SIOS
a
b
0
b
1
bit
The SIOS bit is cleared.
b
2
TMP1940CYAF
to
b
3
complete
b
Read of the received data
4
b
5
the
b
6
ongoing
b
7
b