SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 357

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21. Notations, Precautions and Restrictions
21.1 Notations and Terms
21.2 Precautions and Restrictions
(1) I/O register fields are often referred to as <register_mnemonic>.<field_name> for the interest of
(2) fc, fs, fsys, state
(1) Processor Revision Identifier
(2) BW0–BW1 Pins
(3) Oscillator Warm-Up Counter
(4) Programmable Pullup Resistors
(5) External Bus Mastership
(6) Watchdog Timer (WDT)
(7) A/D Converter (ADC)
(8) Undefined Bits in I/O Registers
brevity. For example, TA01RUN.TA0RUN means the TA0RUN bit in the TA01RUN register.
the SYSCR0.PRCK[1:0] bits are referred to as fperiph and T0 respectively.
0x0000_2C91.
fluctuate during chip operation.
STOP mode triggers the on-chip warm-up counter. The system clock is not supplied to the on-chip logic
until the warm-up counter expires.
disabled under software control. The pullup resistors are not programmable when port pins are
configured as output ports.
after reset. When relevant pins are configured as bus arbitration signals, the I/O peripherals including
the WDT can operate during external bus mastership.
software control. This helps to reduce power dissipation, for example, in STOP mode.
relying on the states of any undefined bits.
The fsys cycle is referred to as a state.
In addition, the clock selected by the SYSCR1.FPSEL bit and the prescalar clock source selected by
The Process Revision Identifier (PRId) register in the TX19 core of the TMP1940CYAF contains
The BW0 and BW1 pins must be connected to the DVcc pin to ensure that their signal levels do not
If an external crystal is utilized, an interrupt signal programmed to bring the TMP1940CYAF out of
When port pins are configured as input ports, the integrated pullup resistors can be enabled and
The relevant port registers must be programmed by using store instructions.
The pin states while the bus is granted to an external device are described in Chapter 7, I/O Ports.
Upon reset, the WDT is enabled. If the watchdog timer function is not required, it must be disabled
The ladder resistor network between the VREFH and VREFL pins can be disconnected under
Undefined I/O register bits are read as undefined states. Therefore, software must be coded without
fosc:
fpll:
fc:
fs:
fgear: Clock selected by the SYSCR1.GEAR[1:0] bits
fsys:
Clock supplied from the X1 and X2 pins
Clock generated by the on-chip PLL
Clock selected by the PLLOFF pin
Clock supplied from the XT1 and XT2 pins
Clock selected by the SYSCR1.SYSCK bit
TMP1940CYAF-315
TMP1940CYAF