SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 43

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.
TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility
of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or
failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs,
please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products
specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability
Handbook.
The products described in this document are subject to foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed
by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result
from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA
CORPORATION or others.
Features
solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction
set of the TX19 includes as a subset the 32-bit instructions of the TX39, which is based on the MIPS R3000A
architecture. Additionally, the TX19 supports the MIPS16 Application-Specific Extensions (ASE) for improved
code density.
suitable for low-voltage, low-power applications.
(1) TX19 core processor
The TX19 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC
The TMP1940 is built on a TX19 core processor and a selection of intelligent peripherals. The TMP1940 is
Features of the TMP1940 include the following:
1)
2)
3)
— High performance
— Low power consumption
Purchase of TOSHIBA I
components in an I
by Philips.
Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed
Combines high performance with low power consumption.
Fast interrupt response suitable for real-time control
The 16-bit ISA is object-code compatible with the code-efficient MIPS16 ASE.
The 32-bit ISA is object-code compatible with the high-performance TX39 family.
Single clock cycle execution for most instructions
3-operand computational instructions for high instruction throughput
5-stage pipeline
On-chip high-speed memory
DSP function: Executes 32-bit x 32-bit multiplier operations with a 64-bit accumulation in a single
clock cycle.
Optimized design using a low-power cell library
Programmable standby modes in which processor clocks are stopped
Distinct starting locations for each interrupt service routine
Automatically generated vectors for each interrupt source
Automatic updates of the interrupt mask level
32-Bit RISC Microprocessor TX19 Family
2
C system, provided that the system conforms to the I
2
C components conveys a license under the Philips I
TMP1940CYAF
TMP1940CYAF-1
2
C Standard Specification as defined
2
C Patent Rights to use these
TMP1940CYAF
980508EBA1
TM