SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 82

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SW00ENB-ZCC

Manufacturer Part Number
SW00ENB-ZCC
Description
MCU, MPU & DSP Development Tools CASEWORKS
Manufacturer
Toshiba
Datasheet

Specifications of SW00ENB-ZCC

Tool Type
Development Software Support
Core Architecture
870
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
7.1
Port 0 (P00–P07)
address/data bus. The P0CR register controls the direction of the Port 0 pins. Upon reset, the P0CR register
bits are cleared, configuring all Port 0 pins as inputs.
register bits all cleared.
Eight Port 0 pins function as either discrete general-purpose I/O pins or the AD[0:7] bits of the
During external memory accesses, Port 0 pins are automatically configured as AD[0:7], with the P0CR
Direction Control
P0CR Write
Output Latch
P0 Write
(bitwise)
Reset
Figure 7.1 Port 0 (P00–P07)
TMP1940CYAF-40
P0 Read
Output Buffer
TMP1940CYAF
Port 0
P00–P07
(AD0–AD7)

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