SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 224

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SC0CR
(0xFFFF_F201)
Name
Read/Write
Reset Value
Function
Note 1: All error flags are cleared to 0 when read.
Note 2: When SCLK0 is configured as an output, the SCLKS bit must be cleared (rising-edge triggered).
Bit 8 of a
received
character
Figure 13.13 SIO0 Control Register (SC0CR)
RB8
7
R
Parity type
0: Odd
1: Even
EVEN
6
0
TMP1940CYAF-182
R/W
Parity
0: Disabled
1: Enabled
PE
5
0
Overrun
OERR
4
0
R (Cleared when read)
1: Error has occurred.
Parity
Input clock in I/O Interface mode
Active edge for the SCLK0 input
Framing error flag
Parity error flag
Overrun error flag
Input clock in I/O Interface mode
PERR
3
0
0
1
0
1
0
1
Baud rate generator
SCLK0 input
Data is transmitted/received
on the SCLK0 rising edge.
Data is transmitted/received
on the SCLK0 falling edge.
Odd parity
Even parity
Framing
TMP1940CYAF
FERR
2
0
These bits are cleared
to 0 when read.
0: SCLK0
1: SCLK0
SCLKS
1
0
R/W
0: Baud rate
1: SCLK0
generator
input
IOC
0
0