SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 366

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note 1: When the Debug Support Unit (DSU) is enabled, all Port A pins function as DSU interface signals, regardless of
Note 2: P37, P85, P86 and P87 should be held at the prescribed logic states for one system clock cycle before and after
P92
SCLK0
CTS
P93
TXD1
P94
RXD1
P95
SCLK1
CTS
P96
XT1
P97
XT2
PA0–PA3
INT1–INT4
PA4
PA5
SCK
PA6
SO
SDA
PA7
SI
SCL
ALE
NMI
BW0–1
TEST
PLLOFF
RESET
VREFH
VREFL
AVCC
AVSS
X1/X2
DVCC,
CVCC,
FVCC
DVSS,
CVSS,
FVSS
Pin Name
0
1
the settings of the Port A Function Register (PAFC) and the Port A Control Register (PACR). Consequently, the
Port A pins can not be configured as INT1–INT4 or Serial Bus Interface (SBI) pins.
the rising edge of RESET , with the RESET signal being stable in either logic state.
# of Pins
1
1
1
1
1
1
4
1
1
1
1
1
1
2
1
1
1
1
1
1
1
2
5
5
Input/output
Input/output
Input
Input/output
Output
Input/output
Input
Input/output
Input/output
Input
Input/output
Input
Input/output
Output
Input/output
Input
Input/output
Input/output
Input/output
Input/output
Output
Input/output
Input/output
Input
Input/output
Output
Input
Input
Input
Input
Input
Input
Input/output
Type
Port 97: Programmable as input or open-drain output
Connection pin for a low-speed crystal
Ports A0–A3: Individually programmable as input or output
Interrupt Request 1–4: Individually programmable to be high-level, low-level, rising-
edge or falling-edge sensitive
Port A4: Programmable as input or output
Port A5: Programmable as input or output
Clock input/output pin when the Serial Bus Interface is in SIO mode
Port A6: Programmable as input or output
Data transmit pin when the Serial Bus Interface is in SIO mode
Data transmit/receive pin when the Serial Bus Interface is in I
as a push-pull or open-drain output
Port A7: Programmable as input or output
Data receive pin when the Serial Bus Interface is in SIO mode
Clock input/output pin when the Serial Bus Interface is in I
programmable as a push-pull or open-drain output
Address Latch Enable (This signal is driven out only when external memory is
accessed.)
Nonmaskable Interrupt Request: Causes an NMI interrupt on the falling edge
Both BW0 and BW1 should be tied to logic 1.
Test pin. This pin should be left open or tied to ground.
This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is
used; otherwise, it should be tied to logic 0.
Reset (with internal pull-up resister): Initializes the whole TMP1940FDBF.
Input pin for high reference voltage for the A/D Converter. This pin should be
connected to the AVCC pin when the A/D Converter is not used.
Input pin for low reference voltage for the A/D Converter. This pin should be connected
to the AVSS pin when the A/D Converter is not used.
Power supply pin for the A/D Converter. This pin should always be connected to power
supply even when the A/D Converter is not used.
Ground pin for the A/D Converter. This pin should always be connected to ground
even when the A/D Converter is not used.
Connection pins for a high-speed crystal
Power supply pins
Ground pins (0 V)
Port 92: Programmable as input or output
Serial Clock Input/Output 0
Serial Clear-to-Send 0
Port 93: Programmable as input or output
Start Serial Transmit Data 1: Programmable as a push-pull or open-drain output
Port 94: Programmable as input or output
Serial Receive Data 1
Port 95: Programmable as input or output
Serial Clock Input/Output 1
Serial Clear-to-Send 1
Port 96: Programmable as input or open-drain output
Connection pin for a low-speed crystal
TMP1940FDBF-8
Function
TMP1940FDBF
2
C mode; as an output,
2
C mode; programmable