SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 211

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SYSCR1.FPSEL
Peripheral Clock
0 (fgear)
1 (fc)
13.2 SIO Components
Note 1: The prescaler's output clock Tn must be selected so that the relationship Tn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
13.2.1
Select
Prescaler
The prescalar clock source ( T0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming
the PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
generator output clock is selected as a serial clock. Table 13.2 shows prescalar output clock resolutions
(@fc = 32 MHz).
64 ( T32).
The SIO0 has a 6-bit prescalar that slows the rate of a clocking source to the serial clock generator.
The serial clock is selectable from several clocks; the prescalar is only enabled when the baud rate
Prescalar output taps can be divide-by-1 ( T0), divide-by-4 ( T2), divide-by-16 ( T8) and divide-by-
SYSCR1.GEAR[1:0]
Clock Gear Value
01 (fc/2)
10 (fc/4)
11 (fc/8)
01 (fc/2)
10 (fc/4)
11 (fc/8)
00 (fc)
00 (fc)
Table 13.2 Prescaler Output Clock Resolutions
SYSCR0.PRCK[1:0]
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
Prescaler Clock
TMP1940CYAF-169
Source
fc/2
fc/2
fc/2
fc/2
fc/2
2
3
4
5
2
(0.125 s) fc/2
(0.25 s) fc/2
(0.5 s)
(1.0 s)
(0.125 s) fc/2
T0
Prescaler Output Clock Resolution
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
4
3
2
5
4
3
6
5
4
7
6
5
4
3
2
4
3
4
(0.5 s)
(0.25 s) fc/2
(0.125 s) fc/2
(1.0 s)
(0.5 s)
(0.25 s) fc/2
(2.0 s)
(1.0 s)
(0.5 s)
(4.0 s)
(2.0 s)
(1.0 s)
(0.5 s)
(0.25 s) fc/2
(0.125 s) fc/2
(0.5 s)
(0.25 s) fc/2
(0.5 s)
T2
TMP1940CYAF
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
6
5
4
7
6
5
8
7
6
9
8
7
6
5
4
6
5
4
6
5
4
6
5
(2.0 s) fc/2
(1.0 s) fc/2
(0.5 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(8.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(16 s) fc/2
(8.0 s) fc/2
(4.0 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(0.5 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(0.5 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
(0.5 s) fc/2
(2.0 s) fc/2
(1.0 s) fc/2
T8
@ fc = 32 MHz
fc/2
8
7
6
9
8
7
10
9
8
11
10
9
8
7
6
8
7
6
8
7
6
8
7
6
T32
(8.0 s)
(4.0 s)
(2.0 s)
(16 s)
(8.0 s)
(4.0 s)
(16 s)
(8.0 s)
(16 s)
(8.0 s)
(4.0 s)
(2.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(8.0 s)
(4.0 s)
(2.0 s)
(32 s)
(64 s)
(32 s)