SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 216

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.2.7
13.2.8
Transmit Counter
transmit counter is also clocked by SIOCLK. The transmitter generates a transimit clock (TXDCLK)
pulse every 16 SIOCLK pulses.
Transmit Controller
The transmit counter is a 4-bit binary up-counter used in UART mode. Like the receive counter, the
TXDCLK
SIOCLK
(i.e., address/data flag) bit for a 9-bit UART character.
to wake up whenever an address character is received. Setting the SC0MOD0.WU bit enables the
wake-up feature. When the SC0CR.RB8 bit has received an address/data flag bit set to 1, the
receiver generates the INTRX0 interrupt.
I/O Interface Mode
controller shifts out each bit in the transmit buffer to the TXD0 pin at the rising edge of the shift
clock driven out on the SCLK0 pin. If the SCLK0 pin is configured as an input by setting the
SC0CR.IOC bit to 1, the transimit controller shifts out each bit in the transmit buffer to the TXD0
pin at either the rising or falling edge of the SCLK0 input, as programmed in the SC0CR.SCLKS
bit.
UART Mode
transmission at the next rising edge of TXDCLK, producing a transmit shift clock (TXDSFT).
The SC0CR.RB8 bit holds the parity bit for an 8-bit UART character and the most-significant bit
In 9-bit UART mode, the receiver wake-up feature allows the slave station in a multidrop system
If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the transimit
Once the CPU loads a character into the transimit buffer, the transmit controller begins
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Figure 13.6 Transimit Clock Generation
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TMP1940CYAF-174
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TMP1940CYAF
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