SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 75

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
6.4
Interrupt
Number
54
55
56
57
58
59
60
61
62
63
Interrupt Detection
EMCGxx field of the IMCGxx register within the CG; in this case, the EIMxx field of the IMCx register
within the INTC has no effect; it must be set to “high-level sensitive,” though. When disabled as a wake-up
singnal, the polarities of INT0–INT4 are programmed in the EIMxx field in the INTC’s IMCx register. The
polarity of INTRTC is always programmed in both the CG and the INTC. All other interrupts are always
programmed in the INTC’s IMCx register.
level-sensitive. When a selected transition is detected, an interrupt request is issued to the INTC (except for
the NMI and INTWDT interrupts, which are directly delivered to the TX19 core processor).
to clear the interrupt condition. INTRTC and INT0–INT4 used for STOP/SLEEP wake-up signaling require
software access to two registers: the EICRCG register in the CG and the INTCLR register in the INTC.
Other interrupts can be cleared by writing its IVR[9:4] value to the INTCLR register located within the
INTC. For an external interrupt configured as level-sensitive, software must explicitly address the device in
question and clear the interrupt condition. A level-sensitive interrupt signal must be held active until the
TX19 core processor reads its interrupt vector from the Interrupt Vector Register (IVR).
Resolving Interrupt Priority
(1) Seven Interrupt Priority Levels
(2) Interrupt Level Notification
(3) Interrupt Vector (Interrupt Source Notification)
When enabled as a STOP/SLEEP wake-up signal, the polarities of INT0–INT4 are programmed in the
Each interrupt source is individually configurable as negative or positive polarity, and as edge-triggered or
It is the responsibility of software (an interrupt handler routine) to determine the cause of an interrupt and
for each interrupt source, which ranges from level 0 to level 7, with level 7 being the highest priority.
Level 0 indicates that the interrupt is disabled.
processor can determine the priority level of an interrupt being requested by reading the IL field in the
CP0 Cause register.
core processor can determine the exact cause of an interrupt by reading the IVR. If multiple interrupt
requests occur at the same level, the interrupt with the smallest interrupt number is delivered (see Table
6.1). When no interrupt is pending, the IVR[9:4] field in the IVR contains a value of zero.
forwards the interrupt vector for that interrupt request. At this time, the TX19 core processor saves the
priority level value in the CMask field of the CP0 Status register.
The Interrupt Mode Control registers (IMCF–IMC0) contain a 3-bit interrupt priority level (ILx) field
When an interrupt event occurs, the INTC sends its priority level to the TX19 core processor. The
Whenever an interrupt request is made, the INTC automatically sets its vector in the IVR. The TX19
When the TX19 core processor responds to a request with an interrupt acknowledge cycle, the INTC
IVR[9:0]
3A0
3B0
3C0
3D0
3E0
360
370
380
390
3F0
INTRX3: SIO receive (Channel 3)
INTTX3: SIO transmit (Channel 3)
INTRX4: SIO receive (Channel 4)
INTTX4: SIO transmit (Channel 4)
INTRTC: RTC
INTAD: A/D conversion complete
INTDMA0: DMA complete (Channel 0)
INTDMA1: DMA complete (Channel 1)
INTDMA2: DMA complete (Channel 2)
INTDMA3: DMA complete (Channel 3)
Interrupt Source
TMP1940CYAF-33
Interrupt Control
Register
IMCDH
IMCEH
IMCFH
IMCEL
IMCFL
TMP1940CYAF
0xFFFF_E03A
0xFFFF_E03C
0xFFFF_E03E
0xFFFF_E036
0xFFFF_E038
Address