SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 397

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(3) The 3rd byte, which the target board receives from the controller, is a command. The code for the
(4) The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the
(5) The 5th to 16th bytes, which the target board receives from the controller, are a 12-byte password.
(6) The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the
RAM Transfer command is 10H.
3rd byte. Before sending back the acknowledge response, the boot program checks for a receive
error. If there was a receive error, the boot program transmits x8H and returns to the state in which
it waits for a command again. In this case, the upper four bits of the acknowledge response are
undefined — they hold the same values as the upper four bits of the previously issued command.
When the SIO0 is configured for I/O Interface mode, the boot program does not check for a
receive error.
If the 3rd byte is equal to any of the command codes listed in Table 3.5 on page 33, the boot
program echoes it back to the controller. When the RAM Transfer command was received, the
boot program echoes back a value of 10H and then branches to the RAM Transfer routine. Once
this branch is taken, a password check is done. Password checking is detailed in Section 3.5.13.
If the 3rd byte is not a valid command, the boot program sends back x1H to the controller and
returns to the state in which it waits for a command again. In this case, the upper four bits of the
acknowledge response are undefined — they hold the same values as the upper four bits of the
previously issued command.
The 5th byte is compared to the contents of address 0x0000_03F4 in the flash memory; the 6th
byte is compared to the contents of address 0x0000_03F5 in the flash memory; likewise, the 16th
byte is compared to the contents of address 0x0000_03FF in the flash memory. If the password
checking fails, the RAM Transfer routine sets the password error flag.
checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the
two’s complement of the total sum. Transmit this checksum value from the controller to the target
board. The checksum calculation is described in details in Section 3.5.15.
UART mode
If the SIO0 can be programmed to the baud rate at which the 1st byte was transferred, the boot
program programs the BR0CR and BR0ADD registers of the SIO0 and sends back 86H to the
controller as an acknowledge. If the SIO0 is not programmable at that baud rate, the boot
program simply aborts with no error indication.
Following the 1st byte, the controller should allow for a time-out period of five seconds. If it
does not receive 86H within the alloted time-out period, the controller should give up the
communication.
The boot program sets the RXE bit in the SC0MOD0 register to enable reception before
loading the SIO transmit buffer with 86H.
I/O Interface mode
The boot program programs the SC0MOD0 and SC0CR registers to configure the SIO0 in I/O
Interface mode (clocked by the rising edge of SCLK0), writes 30H to the SC0BUF and drives
P76 high. Then, the SIO0 waits for the SCLK0 signal to come from the controller. Following
the transmission of the 1st byte, the controller must wait for P76 to go high before sending the
SCLK0 clock to the target board. This must be done at 1/16 the desire baud rate. If the 2nd
byte, which is from the target board to the controller, is 30H, then the controller should take it
as a go-ahead. The controller must then delivers the 3rd byte to the target board at a rate equal
to the desired baud rate. The boot program sets the SC0MOD0.RXE bit to 1 before P76 goes
high (before the target board is to receive the third byte).
TMP1940FDBF-39
TMP1940FDBF