SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 383

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5
Single Boot Mode
TMP1940FDBF on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected
upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash
memory is mapped to an address region different from it (see Figure 3.3 on page 14).
TMP1940FDBF is connected to an external host controller. Via this serial link, a programming routine is
downloaded from the host controller to the TMP1940FDBF on-chip RAM. Then, the flash memory is re-
programmed by executing the programming routine. The host sends out both commands and programming
data to re-program the flash memory.
secure the contents of the flash memory, the validity of the application’s password is checked before a
programming routine is downloaded into the on-chip RAM. If password matching fails, the transfer of a
programming routine itself is aborted.
globally disabled. Even in that case, occurrences of otherwise interrupt-causing events are recorded in the
Interrupt Vector Register (IVR). For example, the SIO receive/transmit status can be checked via the IVR.
The NMI interrupt must also be disabled.
corruption during subsequent Single-Chip (Normal mode) operations. For a detailed description of the erase
and program sequence, refer to Section On-Board Programming and Erasure.
Note: In Single Boot mode, the boot-ROM programs are executed in Normal mode. Don’t change the mode in
In Single Boot mode, the flash memory can be re-programmed by using a program contained in the
Single Boot mode allows for serial programming of the flash memory. Channel 0 of the SIO (SIO0) of the
Communications between the SIO0 and the host must follow the prescribed protocol described later. To
When any on-chip peripherals are utilized in Single Boot mode (such as the SIO), all interrupts must be
Once re-programming is complete, it is recommended to protect relevant flash blocks from accidental
(6) Drive
the programming routine.
Normal mode. After
code.
RESET
(a) Mode Judgment Routine
(b) Transfer Routine
TMP1940FDBF
New Application Program
Flash Memory
[Reset Procedure]
low to reset the TMP1940FDBF. Upon reset, the on-chip flash memory is put in
RESET
Code
TMP1940FDBF-25
is released, the CPU will start executing the new application program
Host Controller
I/O
RAM
Set to Normal mode
0
1 RESET
TMP1940FDBF