SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 364

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2
P00–P07
AD0–AD7
P10–P17
AD8–AD15
A8–A15
P20–P27
A0–A7
A16–A23
P30
RD
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
P36
R
P37
P40
CS
P41
CS
P42
CS2
P43
CS3
P44
SCOUT
P50–P57
AN0–AN7
P70
TA0IN
TXD3
P71
TA1OUT
RXD3
Pin Name
ADTRG
DSU
/
1
0
W
Pin Usage Information
functions for multi-function pins.
Table 2.1 lists the input and output pins of the TMP1940FDBF, including alternate pin names and
# of Pins
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
8
1
1
Input/output
Input/output
Input/output
Input/output
Output
Input/output
Output
Output
Output
Output
Output
Output
Input/output
Output
Input/output
Input
Input/output
Input
Input/output
Output
Input/output
Output
Input/output
Input
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input
Input
Input
Input/output
Input
Output
Input/output
Output
Input
Type
Table 2.1 Pin Names and Functions
Port 0: Individually programmable as input or output
Address (Lower): Bits 0-7 of the address/data bus
Port 1: Individually programmable as input or output
Address/Data (Upper): Bits 8-15 of the address/data bus
Address: Bits 8-15 of the address bus
Port 2: Individually programmable as input or output
Address: Bits 0-7 of the address bus
Address: Bits 16-23 of the address bus
Port 30: Output-only
Read Strobe: Asserted during a read operation from an external memory device
Port 31: Output-only
Write Strobe: Asserted during a write operation on D0-D7
Port 32: Programmable as input or output (with internal pull-up resister)
Higher Write Strobe: Asserted during a write operation on D8-D15
Port 33: Programmable as input or output (with internal pull-up resister)
Wait: Causes the CPU to suspend external bus activity
Port 34: Programmable as input or output (with internal pull-up resister)
Bus Request: Asserted by an external bus master to request bus mastership
Port 35: Programmable as input or output (with internal pull-up resister)
Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to
Port 36: Programmable as input or output (with internal pull-up resister)
Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy
cycle, 0 = write cycle
Port 37: Programmable as input or output (with internal pull-up resister)
DSU Enable: If this pin is sampled low at the rising edge of RESET , the
TMP1940FDBF enters DSU mode for software debugging using an external real-time
debug system. If this pin is sampled as high at the rising edge of RESET , the
TMP1940FDBF enters NORMAL mode.
Port 40: Programmable as input or output (with internal pull-up resister)
Chip Select 0: Asserted low to enable external devices at programmed addresses
Port 41: Programmable as input or output (with internal pull-up resister)
Chip Select 1: Asserted low to enable external devices at programmed addresses
Port 42: Programmable as input or output (with internal pull-up resister)
Chip Select 2: Asserted low to enable external devices at programmed addresses
Port 43: Programmable as input or output (with internal pull-up resister)
Chip Select 3: Asserted low to enable external devices at programmed addresses
Port 44: Programmable as input or output
System Clock Output: Drives out a clock signal at the same frequency as the CPU
clock (high-speed or low-speed)
Port 5: Input-only
Analog Input: Input to the on-chip A/D Converter
A/D Trigger: Starts an A/D conversion (multiplexed with P53)
Port 70: Programmable as input or output
8-Bit Timer 0 Input: Input to Timer 0
Serial Transmit Data 3: Programmable as a push-pull or open-drain output
Port 71: Programmable as input or output
8-Bit Timer 1 Output: Output from either Timer 0 or Timer 1
Serial Receive Data 3
BUSRQ
TMP1940FDBF-6
.
Function
TMP1940FDBF