AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 219

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

26.4.2.4
26.4.2.5
26.4.2.6
Figure 26-5. Receiver Ready
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the
RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared
when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
Figure 26-6. Receiver Overrun
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with
the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit
PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register
DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status
command is written, the PARE bit remains at 1.
Figure 26-7. Parity Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop
bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same
time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit
RSTSTA at 1.
Receiver Overrun
Parity Error
Receiver Framing Error
RXRDY
RXRDY
RXRDY
OVRE
DRXD
DRXD
PARE
DRXD
S
S
S
D0
D0
D0
D1
D1
D1
D2
D2
D2
D3
D3
D3
D4
D4
D5
D5
D4
D6
D6
D5
D7
D7
D6
P
P
Wrong Parity Bit
D7
stop
P
S
S
stop
Read DBGU_RHR
D0
D0
D1
D1
D2
D2
D3
D3
RSTSTA
SAM7S Series [DATASHEET]
D4
D4
D5
D5
D6
D6
D7
D7
6175M–ATARM–26-Oct-12
P
P
stop
RSTSTA
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