AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 220

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

26.4.3
26.4.3.1
26.4.3.2
26.4.3.3
Figure 26-8. Receiver Framing Error
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmit-
ter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter
waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the
transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a
character has been written in the Transmit Holding Register, the characters are completed before the transmitter is
actually stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1.
This immediately stops the transmitter, whether or not it is processing characters.
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the
format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8
data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out
as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity
bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed
space or mark bit.
Figure 26-9. Character Transmission
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The
transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the writ-
ten character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second
character is written in DBGU_THR. As soon as the first character is completed, the last character written in
DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have
been processed, the bit TXEMPTY rises after the last stop bit has been completed.
Transmitter
Transmitter Reset, Enable and Disable
Transmit Format
Transmitter Control
Baud Rate
Example: Parity enabled
FRAME
RXRDY
DRXD
DTXD
Clock
S
D0
Start
Bit
D1
D2
D0
D3
D4
D1
D5
D2
D6
D7
D3
P
Detected at 0
Stop Bit
stop
D4
D5
RSTSTA
D6
SAM7S Series [DATASHEET]
D7
Parity
Bit
6175M–ATARM–26-Oct-12
Stop
Bit
220