AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 24

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

8.8.3.6 SAM7S161/16
Table 8-1.
8.8.4
8.8.5
Device
SAM7S512
SAM7S256
SAM7S128
SAM7S64
SAM7S321/32
SAM7S161/16
The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or
programming commands. The SAM7S161/16 contains 8 lock regions and each lock region contains 32 pages of 64
bytes. Each lock region has a size of 2 Kbytes.
If a locked-region’s erase or program command occurs, the command is aborted and the LOCKE bit in the MC_FSR
register rises and the interrupt line rises if the LOCKE bit has been written at 1 in the MC_FMR register.
The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
Table 8-1
Security Bit Feature
The SAM7S Series features a security bit, based on a specific NVM Bit. When the security is enabled, any access to the
Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the
confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the
security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the
security bit is deactivated, all accesses to the flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is
safer to connect it directly to GND for the final application.
Non-volatile Brownout Detector Control
Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a
power loss, the brownout detector operations remain in their state.
These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and
“Set General-purpose NVM Bit” of the EFC User Interface.
Flash Configuration Summary
GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it
disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.
The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1
enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset.
Asserting ERASE disables the brownout reset by default.
summarizes the configuration of the eight devices.
Number of Lock Bits
32
16
8
16
8
8
64
64
64
32
32
32
Number of Pages in the Lock Region
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
Page Size
256 bytes
256 bytes
256 bytes
128 bytes
128 bytes
64 bytes
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