AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 614

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.5.9.5
40.6
40.6.1
40.6.1.1
40.6.2
40.6.2.1
40.6.2.2
40.6.2.3
40.6.2.4
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken
into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state
machine will go in idle mode and enable the RXBRK flag.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
SAM7S256 Errata - Manufacturing Number 58818C
Refer to
Important:
The Chip ID is 0x270D0940 instead of 0x270B0940.
None.
The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any
ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag.
None
When reading LCDR at the same instant as an end of conversion, with DRDY already active, DRDY is kept active
regardless of the enable status of the current channel. This sets DRDY, whereas new data is not stored.
None
Reading CDR for channel “y” at the same instant as an end of conversion on channel “x” with EOC[x] already
active, leads to skipping to set the DRDY flag if channel “x” is enabled.
Use of DRDY functionality with access to CDR registers should be avoided.
DRDY does not rise when disabling channel “y” at the same time as an end of “x” channel conversion, although
data is stored into CDRx and LCDR.
None.
Chip ID
Analog-to-Digital Converter (ADC)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
USART: DCD is active High instead of Low
Wrong Chip ID Value
ADC: DRDY Bit Cleared
ADC: DRDY not Cleared on Disable
ADC: DRDY Possibly Skipped due to CDR Read
ADC: Possible Skip on DRDY when Disabling a Channel
Section 40.1 “Marking” on page
Section 40.6.14.1 ”WDT: The Watchdog Timer May Lock the Device in a Reset State”
595.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
614