AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 42
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Part Number:
AT91SAM7S256D-AU
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11.2
11.2.1
11.2.2
11.2.3
11.2.4
ARM7TDMI Processor
For further details on ARM7TDMI, refer to the following ARM documents:
ARM Architecture Reference Manual (DDI 0100E)
ARM7TDMI Technical Reference Manual (DDI 0210B)
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-
byte boundaries and half words to two-byte boundaries.
Unaligned data access behavior depends on which instruction is used where.
The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:
Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are
entered in order to service interrupts or exceptions, or to access protected resources.
The ARM7TDMI processor has a total of 37registers:
These registers are not accessible at the same time. The processor state and operating mode determine which
registers are available to the programmer.
At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception
processing.
Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current
instruction.
R14 holds the return address after a subroutine call.
R13 is used (by software convention) as a stack pointer.
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical regis-
ter in all processor modes. They are general-purpose registers, with no special uses managed by the architecture,
and can be used wherever an instruction allows a general-purpose register to be specified.
• 31 general-purpose 32-bit registers
• 6 status registers
Instruction Type
Data Type
ARM7TDMI Operating Mode
ARM7TDMI Registers
User: The normal ARM program execution state
FIQ: Designed to support high-speed data transfer or channel process
IRQ: Used for general-purpose interrupt handling
Supervisor: Protected mode for the operating system
Abort mode: Implements virtual memory and/or memory protection
System: A privileged user mode for the operating system
Undefined: Supports software emulation of hardware coprocessors
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
42
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