AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 507

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

35.5.2
35.5.2.1
Figure 35-4. Control Read and Write Sequences
Notes:
Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be per-
formed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible
by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the
USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction
which follows the setup transaction. These requests may also return data. The data is carried out to the host by the
next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer.
When a setup transfer is received by the USB endpoint:
Thus, firmware must detect the RXSETUP polling the UDP_ CSRx or catching an interrupt, read the setup packet
in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the
FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the
FIFO.
• The USB device automatically acknowledges the setup packet
• RXSETUP is set in the UDP_ CSRx register
• An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the
Handling Transactions with USB V2.0 Device Peripheral
microcontroller if interrupts are enabled for this endpoint.
Setup Transaction
1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no
device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more informa-
tion on the protocol layer.
data).
Control Read
Control Write
No Data
Control
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
Status Stage
Status IN TX
Data OUT TX
Data IN TX
Data Stage
Data Stage
Data OUT TX
Data IN TX
SAM7S Series [DATASHEET]
Status OUT TX
Status Stage
Status IN TX
Status Stage
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