AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 542

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AT91SAM7S256D-AU

Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet

Specifications of AT91SAM7S256D-AU

Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm

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36.5.4
Figure 36-2. EOCx and DRDY Flag Behavior
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register
(ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC
channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY
bit and the EOC bit corresponding to the last converted channel.
CHx
Conversion Results
Write the ADC_CR
with START = 1
Conversion Time
Read the ADC_CDRx
Write the ADC_CR
with START = 1
SAM7S Series [DATASHEET]
Conversion Time
6175M–ATARM–26-Oct-12
Read the ADC_LCDR
542

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