AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 37

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

10.5
10.6
10.7
Serial Peripheral Interface
Two-wire Interface
USART
Supports communication with external serial devices
Master or slave serial peripheral bus interface
Master Mode only (SAM7S512/256/128/64/321/32)
Master, Multi-Master and Slave Mode support (SAM7S161/16)
General Call supported in Slave Mode (SAM7S161/16)
Compatibility with
One, two or three bytes internal address registers for easy Serial Memory access
7-bit or 10-bit slave addressing
Sequential read/write operations
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
IrDA modulation and demodulation
Test Modes
Four chip selects with external decoder allow communication with up to 15 peripherals
Serial memories, such as DataFlash
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External co-processors
8- to 16-bit programmable data length per chip select
Programmable phase and polarity per chip select
Programmable transfer delays between consecutive transfers and between clock and data per chip select
Programmable delay between consecutive transfers
Selectable mode fault detection
Maximum frequency at up to Master Clock
1, 1.5 or 2 stop bits in Asynchronous Mode
1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB or LSB first
Optional break generation and detection
By 8 or by 16 over-sampling receiver frequency
Hardware handshaking RTS - CTS
Modem Signals Management DTR-DSR-DCD-RI on USART1 (not present on SAM7S32/16)
Receiver time-out and transmitter timeguard
Multi-drop Mode with address generation and detection
NACK handling, error counter with repetition and iteration limit
Communication at up to 115.2 Kbps
Remote Loopback, Local Loopback, Automatic Echo
I
2
C
compatible devices (refer to the TWI sections of the datasheet)
®
and 3-wire EEPROMs
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
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