AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 272
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AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Price
Company:
Part Number:
AT91SAM7S256D-AU
Manufacturer:
ATMEL
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101
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28.6
28.6.1
28.6.2
Functional Description
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to
NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the
MOSI line driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output,
the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver.
The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not
driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated
only in Master Mode.
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters
determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two
possible states, resulting in four possible combinations that are incompatible with one another. Thus, a mas-
ter/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in
different configurations, the master must reconfigure itself each time it needs to communicate with a different slave.
Table 28-2
Table 28-2.
Figure 28-3
Modes of Operation
Data Transfer
shows the four modes and corresponding parameter settings.
and
SPI Bus Protocol Mode
Figure 28-4
SPI Mode
0
1
2
3
show examples of data transfers.
CPOL
0
0
1
1
SAM7S Series [DATASHEET]
NCPHA
1
0
1
0
6175M–ATARM–26-Oct-12
272
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