AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 343

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

30.9.5.5
Figure 30-29. Repeated Start + Reversal from Read to Write Mode
Figure 30-30. Repeated Start + Reversal from Write to Read Mode
Notes:
TWI_RHR
TWI_RHR
TWI_THR
TWI_THR
TXCOMP
TXCOMP
EOSACC
EOSACC
SVREAD
SVREAD
Reversal of Read to Write
Reversal of Write to Read
RXRDY
RXRDY
SVACC
SVACC
TXRDY
TXRDY
TWD
TWD
The master initiates the communication by a read command and finishes it by a write command.
Figure 30-29 on page 343
1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
The master initiates the communication by a write command and finishes it by a read
page 343
1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
the ACK.
Reversal after a Repeated Start
S
S
describes the repeated start + reversal from Write to Read mode.
As soon as a START is detected
As soon as a START is detected
SADR
SADR
W
R
Read TWI_RHR
A
A
DATA0
describes the repeated start + reversal from Read to Write mode.
DATA0
DATA0
A
A
DATA0
DATA1
DATA1
DATA1
NA
A
DATA1
Sr
Sr
SADR
SADR
Cleared after read
Cleared after read
R
W
DATA2
A
A
SAM7S Series [DATASHEET]
DATA2
DATA2
command.Figure 30-30 on
DATA2
A
A
6175M–ATARM–26-Oct-12
DATA3
DATA3
DATA3
DATA3
NA
A
P
P
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