AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 325

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 30-10. Master Read with Multiple Data Bytes
30.7.6
30.7.6.1
TXCOMP
RXRDY
TWD
nal address (IADR), the STOP bit must be set after the next-to-last data received. See
Address usage see
Figure 30-9. Master Read with One Data Byte
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave
address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or
write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example.
When performing read operations with an internal address, the TWI performs a write operation to set the internal
address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after
sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 30-11
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0.
In the figures below the following abbreviations are used:
Internal Address
• S
• Sr
• P
• W
• R
• A
S
7-bit Slave Addressing
Write START Bit
DADR
and
Start
Repeated Start
Stop
Write
Read
Acknowledge
Figure 30-13
Section
R
TXCOMP
RXRDY
TWD
A
30.7.6.
for Master Write operation with internal address.
DATA n
S
Write START &
STOP Bit
DADR
Read RHR
A
DATA n
DATA (n+1)
R
A
A
DATA (n+1)
Read RHR
DATA (n+m)-1
DATA
SAM7S Series [DATASHEET]
Read RHR
N
DATA (n+m)-1
A
Read RHR
after next-to-last data read
P
DATA (n+m)
Write STOP Bit
Figure
6175M–ATARM–26-Oct-12
30-10. For Internal
Figure
N
DATA (n+m)
30-12. See
Read RHR
P
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