AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 509

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 35-6. Data IN Transfer for Non Ping-pong Endpoint
35.5.2.4
USB Bus Packets
TXPKTRDY Flag
(UDP_CSRx)
TXCOMP Flag
(UDP_CSRx)
FIFO (DPR)
Content
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows han-
dling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a
constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the
current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the
microcontroller, the other one is locked by the USB device.
Figure 35-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte
Using Endpoints With Ping-pong Attribute
endpoint’s UDP_ CSRx register.
values in the endpoint’s UDP_ FDRx register.
Set by the firmware
Data IN
PID
Prevous Data IN TX
Data IN 1
Interrupt Pending
Microcontroller
1 st Data Payload
2 nd Data Payload
3 rd Data Payload
Cleared by Hw
Data IN 1
DPR access by the firmware
ACK
PID
Load In Progress
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Set by the firmware
Microcontroller Load Data in FIFO
Write
Data IN
PID
USB Device
NAK
PID
Cleared by Firmware
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
Data IN
PID
DPR access by the hardware
Data is Sent on USB Bus
USB Bus
Data IN 2
SAM7S Series [DATASHEET]
Payload in FIFO
2 nd Data Payload
3 rd Data Payload
1 st Data Payload
Data IN 2
Data IN Packet
Data IN Packet
Data IN Packet
Cleared by Hw
6175M–ATARM–26-Oct-12
ACK
PID
Cleared by
Firmware
Interrupt
Pending
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