AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 607

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.5.1.4
40.5.1.5
40.5.1.6
40.5.1.7
40.5.1.8
40.5.1.9
DRDY does not rise when disabling channel “y” at the same time as an end of “x” channel conversion, although
data is stored into CDRx and LCDR.
None.
Read of the Status Register at the same instant as an end of conversion leads to skipping the update of the
GOVRE (general overrun) flag. GOVRE is neither reset nor set.
For example, if reading the status while an end of conversion is occurring and:
None
When reading CDRy (Channel Data Register y) at the same instant as an end of conversion on channel “x” with the
following conditions:
GOVRE should be set but is not.
None
When disabling channel “y” at the same instant as an end of conversion on channel “x”, EOC[x] and DRDY being
already active, GOVRE does not rise.
Note:
None
When the OVRE flag (on channel i) has been set but the related EOC status (of channel i) has been cleared (by a
read of CDRi or LCDR), reading the Status register at the same instant as an end of conversion (causing the set of
EOC status on channel i), does not lead to a reset of the OVRE flag (on channel i) as expected.
None
If a channel is disabled while a conversion is running and if a read of CDR is performed at the same time as an end
of conversion of any channel occurs, the EOC of the channel with the conversion running may rise (whereas it has
been disabled).
1. GOVRE is active but DRDY is inactive, does not correspond to a new general overrun condition but the
2. GOVRE is inactive but DRDY is active, does correspond to a new general overrun condition but the
• EOC[x] already active,
• DRDY already active,
• GOVRE inactive,
• previous data stored in LCDR being neither data from channel “y”, nor data from channel “x”.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
ADC: Possible Skip on DRDY when Disabling a Channel
ADC: GOVRE Bit is not Updated
ADC: GOVRE Bit is not Set when Reading CDR
ADC: GOVRE Bit is not Set when Disabling a Channel
ADC: OVRE Flag Behavior
ADC: EOC Set although Channel Disabled
GOVRE flag is not reset.
GOVRE flag is not set.
OVRE[x] rises as expected.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
607