AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 373

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

31.6.3.5
The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR).
The PAR field also enables the Multidrop mode, see
ation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the
character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the
number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is
selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is
even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s
and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity gener-
ator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the
parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0
for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled,
the transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 31-6
figuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a
parity is even.
Table 31-6.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register
(US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
31-14
Figure 31-14. Parity Error
Character
Parity
illustrates the parity bit status setting and clearing.
A
A
A
A
A
shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the con-
Parity Bit Examples
Baud Rate
RXRDY
US_CR
PARE
Clock
Write
RXD
Hexa
0x41
0x41
0x41
0x41
0x41
Start
Bit
D0
D1
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Binary
D2
D3
D4
“Multidrop Mode” on page
D5
D6
D7
Parity Bit
Parity
Bad
None
Bit
1
0
1
0
Stop
Bit
SAM7S Series [DATASHEET]
374. Even and odd parity bit gener-
Parity Mode
RSTSTA = 1
Space
Even
None
Mark
Odd
6175M–ATARM–26-Oct-12
Figure
373