AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 757

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Version
6175H
Comments
Overview:
“Features” on page 1
See:
Section 8.6 “SAM7S161/16” on page
Section 9.5 ”Debug Unit”
Section 6. ”I/O Lines
ADC:
AIC:
Debug and Test:
Table 12-2, “SAM7S Series Debug Unit Chip ID,” on page
Table 12.5.5, “ID Code Register,” on page
EFC:
FFPI:
Table
Global update to terms listed below: ≥
Fuse → GPNVM
SFB → SGPB
CFB → CGPB
GFB → GGPB
Section 20.2.5.6 on page 133 &Section 20.3.4.6 on page
PIO:
Section 27.4.5 ”Synchronous Data
PIO User Interface,
PMC:
SPI:
SSC:
TC:
463
updated with indexed offset.
Section 33.6.4 ”TC Channel Mode Register: Capture
TWI:
Section 29. ”Two-wire Interface (TWI)
Important changes to this datasheet include a clarification of Atmel TWI compatibility with I2C Standard.
Section 30. ”Two Wire Interface (TWI)
AT91SAM7S16/161 devices.
PWM:
Section 34.6 ”Pulse Width Modulation Controller (PWM) User
“Register
from:
Section 33.6 ”Timer Counter (TC) User
and register offsets indexed.
Section 28.6.4 ”SPI Slave
Section 23.8.15 ”AIC Spurious Interrupt Vector
Table 1-1, “Configuration Summary,” on page 3
Section 19.3.3 ”MC Flash Status Register”
Section 34.6.10 on page 497
“SSC Receive Clock Mode Register” on page
Section 36.6.2 ”ADC Mode
20-6,
Figure 24-2 ”Typical Crystal Connection”
Mapping”, the PWM channel-dependent registers are indexed. See also, PWM Channel registers
Table 20-7
Table 27-2, “Register Mapping”
Considerations”, JTAG Port Pin, Test Pin, Erase Pin, updated.
(and all of datasheet) Added AT91SAM7S16/161 to product family.
plus
Chip ID updated.
Table
Mode”, Corrected information on OVRES (SPI_SR) and data read in SPI_RDR. 3943
Section 33.6.3 on page 466
Register”, STARTUP and PRESCAL bitfields updated (width expanded).
20-8,
Output”, typo fixed on PIO_OWSR
to
19.
Section 34.6.13 on page
SAM7S512/256/128/64/321/32”, section has been updated.
SAM7S161/16”, section added specific to the TWI implementation on the
Table
56, updated.
Interface”, register mapping consolidated in
plus
updated
GPNVM2 removed from bit field 10.
updates to footnotes, PIO_PSR, PIO_ODSR, PIO_PDSR
426, typo corrected in STTDLY bit field.
Table
Register”, bitfield typo corrected
Mode”, bit field 15 and WAVE bit field description updated.
141, security bit restraint on access to FFPI explained
20-17,
51, updated.
to
Interface”, in the Offset column in
499.
Section 33.6.13 on page
Table 20-18
and
SAM7S Series [DATASHEET]
Table 20-20
Table 33-4 on page
480, register names
updated
Table 34-2,
6175M–ATARM–26-Oct-12
Change
Request
Ref.
rfo
4325
5063
4749
4325/rfo
4464
4410
3933
4744
3289
3974
3861
4478
4583
4247
rfo
4486
757