AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 452

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

33.5.4
33.5.5
33.5.6
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped.
See
•
•
Figure 33-4. Clock Control
Each channel can independently operate in two different modes:
•
•
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the
external trigger.
A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a
fourth external trigger is available to each mode.
The following triggers are common to both modes:
•
Clock Control
TC Operating Modes
Trigger
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control
Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In
Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When
disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-
enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the
clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC
compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect
only if the clock is enabled.
Capture Mode provides measurement on signals.
Waveform Mode provides wave generation.
Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
Figure
33-4.
Selected
Counter
Clock
Clock
Q
R
S
Trigger
CLKSTA
Q
CLKEN
S
R
Event
Stop
CLKDIS
SAM7S Series [DATASHEET]
Disable
Event
6175M–ATARM–26-Oct-12
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