AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 378

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 31-18. Break Transmission
31.6.3.11
31.6.3.12
Baud Rate
TXEMPTY
US_CR
TXRDY
Clock
Write
TXD
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data at 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writ-
ing the Control Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode
or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK
bit.
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to con-
nect with the remote device, as shown in
Figure 31-19. Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the
Mode Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchro-
nous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the
CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC
channel for reception. The transmitter can handle hardware handshaking in any case.
Figure 31-20
the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Nor-
mally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the
Receive Break
Hardware Handshaking
Start
Bit
D0
D1
shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if
D2
STTBRK = 1
D3
D4
D5
D6
D7
USART
Parity
Bit
RXD
Stop
TXD
CTS
RTS
Bit
Figure
31-19.
Break Transmission
STPBRK = 1
RXD
TXD
RTS
CTS
Remote
Device
SAM7S Series [DATASHEET]
End of Break
6175M–ATARM–26-Oct-12
378