AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 246

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 27-5. Input Glitch Filter Timing
27.4.10
Figure 27-6. Input Change Interrupt Timings
27.5
if PIO_IFSR = 0
if PIO_IFSR = 1
Read PIO_ISR
PIO_PDSR
PIO_PDSR
Pin Level
Pin Level
PIO_ISR
I/O Lines Programming Example
MCK
Input Change Interrupt
MCK
The PIO Controller can be programmed to generate an interrupt when it detects an input change
on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable
Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the
input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask
Register). As Input change detection is possible only by comparing two successive samplings of
the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is
available, regardless of the configuration of the I/O line, i.e. configured as an input only, con-
trolled by the PIO Controller or assigned to a peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt
Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt
line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to gen-
erate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that
all the interrupts that are pending when PIO_ISR is read must be handled.
The programing example as shown in
configuration.
1 cycle
• 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain,
with pull-up resistor
1 cycle
APB Access
up to 1.5 cycles
Table 27-1
1 cycle
up to 2.5 cycles
2 cycles
below is used to define the following
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
APB Access
up to 2 cycles
1 cycle
1 cycle
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