AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 342

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

Figure 30-28. Clock Synchronization in Write Mode
Notes:
Clock Synchronization in Write Mode
TWI_RHR
TXCOMP
SVREAD
SCLWS
RXRDY
SVACC
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was
not detected, it is tied low until TWI_RHR is read.
Figure 30-28 on page 342
TWCK
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
TWD
SADR.
nism is finished.
S
SADR
As soon as a START is detected
W
describes the clock synchronization in Read mode.
A
DATA0
CLOCK is tied low by the TWI as long as RHR is full
A
DATA1
DATA0 is not read in the RHR
SCL is stretched on the last bit of DATA1
Rd DATA0
SAM7S Series [DATASHEET]
A
Rd DATA1
DATA1
DATA2
6175M–ATARM–26-Oct-12
NA
Rd DATA2
DATA2
S
ADR
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