AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 380

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

31.6.4.2
Figure 31-23. T = 0 Protocol without Parity Error
Figure 31-24. T = 0 Protocol with Parity Error
31.6.4.3
Baud Rate
Baud Rate
Clock
CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in nor-
mal or inverse mode. Refer to
The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirec-
tional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver
or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode
may lead to unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted
on the I/O line at their negative value. The USART does not support this format and the user has to perform an
exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the
Receive Holding Register (US_RHR).
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which
lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with
the transmission of the next character, as shown in
If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in
24. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as
the guard time length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive
Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software
can handle the error.
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER)
register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the
NB_ERRORS field.
I/O
Clock
RXD
Protocol T = 0
Receive Error Counter
Start
Bit
Start
Bit
D0
D0
D1
D1
D2
“USART Mode Register” on page 390
D2
D3
D3
D4
D4
D5
Figure
D5
D6
31-23.
D6
D7
D7
Parity
and
Bit
Parity
“PAR: Parity Type” on page
Bit
Time 1
Guard
SAM7S Series [DATASHEET]
Time 1
Guard
Error
Time 2
Guard
Time 2
Guard
6175M–ATARM–26-Oct-12
Next
Start
Bit
Start
Bit
Repetition
392.
D0
Figure 31-
D1
380