AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 489

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

34.5.3.4
34.6
Table 34-2.
Note:
Offset
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x4C - 0xFC
0x100 - 0x1FC
0x200 + ch_num * 0x20 + 0x00
0x200 + ch_num * 0x20 + 0x04
0x200 + ch_num * 0x20 + 0x08
0x200 + ch_num * 0x20 + 0x0C
0x200 + ch_num * 0x20 + 0x10
(1)
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the correspond-
ing channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is dis-
abled by setting the corresponding bit in the PWM_IDR register.
Pulse Width Modulation Controller (PWM) User Interface
1. Some registers are indexed with “ch_num” index ranging from 0 to X-1.
Interrupts
Register Mapping
Reserved
Register
PWM Mode Register
PWM Enable Register
PWM Disable Register
PWM Status Register
PWM Interrupt Enable Register
PWM Interrupt Disable Register
PWM Interrupt Mask Register
PWM Interrupt Status Register
Reserved
PWM Channel Mode Register
PWM Channel Duty Cycle Register
PWM Channel Period Register
PWM Channel Counter Register
PWM Channel Update Register
Name
PWM_ENA
PWM_SR
PWM_IDR
PWM_IMR
PWM_ISR
PWM_CCNT
PWM_MR
PWM_DIS
PWM_IER
PWM_CMR
PWM_CDTY
PWM_CPRD
PWM_CUPD
–
SAM7S Series [DATASHEET]
Read/Write
Read/Write
Read/Write
Read/Write
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Write-only
Access
6175M–ATARM–26-Oct-12
–
Reset
0x0
0x0
0x0
0x0
0
0
0
0
–
-
-
-
-
-
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