AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 619

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.6.8
40.6.8.1
40.6.8.2
40.6.9
40.6.9.1
40.6.9.2
40.6.9.3
40.6.9.4
Do not disable a channel before completion of one period of the selected clock.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the cor-
responding bit might be cleared. This can lead to the loss of this event.
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
Under certain rare circumstances, the Real-time Timer Value (RTT_VR) may be corrupted.
Use RTTINC as an increment for a software counter.
If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on
the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been
transferred in the shifter. This can imply for example, that the second data is sent twice.
Do not use the combination CSAAT = 1 and SCBR = 1.
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in
the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes a “1” in the bit 24 (LASTXFER bit) of
the SPI_TDR, the chip select will rise as soon as the TXEMPTY flag is set.
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers.
SPCK pin can toggle out before the first transfer in Master Mode.
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers.
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output
spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the
selected Chip select is. For example, if SPI_CSR0 is configured for a 10-bit transfer whereas SPI_CSR1 is config-
ured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC, on Chip select 1, the
transfer will be considered as a HalfWord transfer.
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the
SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of the CSRy Register.
Real Time Timer (RTT)
Serial Peripheral Interface (SPI)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
RTT: Possible Event Loss when Reading RTT_SR
RTT: RTT_VR May be Corrupted
SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1
SPI: LASTXFER (Last Transfer) Behavior
SPI: SPCK Behavior in Master Mode
SPI: Chip Select and Fixed Mode
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
619