AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 606

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

40.4.9.3
40.4.9.4
40.4.9.5
40.5
40.5.1
40.5.1.1
40.5.1.2
40.5.1.3
The XOFF character is sent only when the receive buffer is detected full. While the XOFF is being sent, the remote
transmitter is still transmitting. As only one Holding register is available in the receiver, characters will be lost in
reception. This makes the software handshaking functionality ineffective.
None.
In receiver mode, when there are two consecutive characters (without timeguard in between), RXBRK is not taken
into account. As a result, the RXBRK flag is not enabled correctly and the frame error flag is set.
Constraints on the transmitter device connected to the SAM7S USART receiver side:
The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken
into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state
machine will go in idle mode and enable the RXBRK flag.
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Add an inverter.
SAM7S512 Errata - Revision B Parts
Refer to
Note: AT91SAM7S512 Revision B chip ID is: 0x270B 0A4F.
The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any
ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag.
None
When reading LCDR at the same instant as an end of conversion, with DRDY already active, DRDY is kept active
regardless of the enable status of the current channel. This sets DRDY, whereas new data is not stored.
None
Reading CDR for channel “y” at the same instant as an end of conversion on channel “x” with EOC[x] already
active, leads to skipping to set the DRDY flag if channel “x” is enabled.
Use of DRDY functionality with access to CDR registers should be avoided.
Analog-to-Digital Converter (ADC)
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround:
Problem Fix/Workaround
Problem Fix/Workaround
USART: XOFF Character Bad Behavior
USART: RXBRK Flag Error in Asynchronous Mode
USART: DCD is active High instead of Low
ADC: DRDY Bit Cleared
ADC: DRDY not Cleared on Disable
ADC: DRDY Possibly Skipped due to CDR Read
Section 40.1 “Marking” on page
595.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
606