AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 277

• Manufacturer Part Number: AT91SAM7S256D-AU
• Description: ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
• Manufacturer: Atmel
• Series: SAM7S256r

Specifications of AT91SAM7S256D-AU

• Rohs: yes
• Core: ARM
• Processor Series: AT91SAM
• Data Bus Width: 16 bit/32 bit
• Maximum Clock Frequency: 55 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• Interface Type: 2-Wire, I2S, SPI, USART
• Length: 7 mm

28.6.3.4
Figure 28-7. Programmable Delays
28.6.3.5
Chip Select 1
Chip Select 2
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK
divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable
results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the
Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral with-
out reprogramming.
Figure 28-7
can be programmed to modify the transfer waveforms:
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS
signals are high before and after each transfer.
The peripheral selection can be performed in two different ways:
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the cur-
rent peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the cur-
rent peripheral. This means that the peripheral selection can be defined for each new data.
• The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in
• The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows
• The delay between consecutive transfers, independently programmable for each chip select by writing the
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new
one.
the start of SPCK to be delayed after the chip select has been asserted.
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
Transfer Delays
Peripheral Selection
SPCK
shows a chip select transfer change and consecutive transfers on the same chip select. Three delays
DLYBCS
DLYBS
DLYBCT
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
DLYBCT
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