AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 328

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AT91SAM7S256D-AU

Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet

Specifications of AT91SAM7S256D-AU

Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm

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30.7.7
The following flowcharts shown in
17 on page
tions. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the
interrupt enable register (TWI_IER) be configured first.
Figure 30-14. TWI Write Operation with Single Data Byte without Internal Address
Read-write Flowcharts
331,
Figure 30-18 on page 332
Figure
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Device slave address (DADR)
30-14,
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Write ==> bit MREAD = 0
TWI_THR = Data to send
and
Set the Control register:
Load Transmit register
- Transfer direction bit
Read Status register
Read Status register
(Needed only once)
Transfer finished
- Master enable
TXCOMP = 1?
Set TWI clock
TXRDY = 1?
Yes
Figure 30-19 on page 333
Yes
Figure 30-15 on page
BEGIN
329,
No
No
give examples for read and write opera-
SAM7S Series [DATASHEET]
Figure 30-16 on page
6175M–ATARM–26-Oct-12
330,
Figure 30-
328

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