AT91SAM7S256D-AU Atmel, AT91SAM7S256D-AU Datasheet - Page 298
AT91SAM7S256D-AU
Manufacturer Part Number
AT91SAM7S256D-AU
Description
ARM Microcontrollers - MCU 256K Flash SRAM 64K ARM based MCU
Manufacturer
Atmel
Series
SAM7S256r
Datasheet
1.AT91SAM7S256D-AU.pdf
(775 pages)
Specifications of AT91SAM7S256D-AU
Rohs
yes
Core
ARM
Processor Series
AT91SAM
Data Bus Width
16 bit/32 bit
Maximum Clock Frequency
55 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
LQFP-64
Mounting Style
SMD/SMT
Interface Type
2-Wire, I2S, SPI, USART
Length
7 mm
Available stocks
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Price
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Part Number:
AT91SAM7S256D-AU
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ATMEL
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29.6.3
Figure 29-6. Master Write with Multiple Data Byte
TXCOMP
TXRDY
TWD
Master Transmitter Mode
Write THR (Data n)
S
DADR
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this
mode, it generates the clock according to the value programmed in the Clock Waveform Gener-
ator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the
interface to be adapted to a wide range of clocks.
After the master initiates a Start condition when writing into the Transmit Holding Register,
TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in
TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer
direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in
the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR. When no more data is written
into the TWI_THR, the master generates a stop condition to end the transfer. The end of the
complete transfer is marked by the TWI_TXCOMP bit set to one. See
and
Figure 29-5. Master Write with One Data Byte
• Master transmitter mode
• Master receiver mode
Figure
W
TXCOMP
TXRDY
TWD
29-7.
A
Write THR (DATA)
S
Write THR (Data n+1)
DATA n
DADR
A
W
A
Write THR (Data n+x)
DATA n+5
Last data sent
DATA
SAM7S Series [DATASHEET]
A
(ACK received and TXRDY = 1)
A
DATA n+x
STOP sent automaticaly
(ACK received and TXRDY = 1)
P
STOP sent automaticaly
Figure
6175M–ATARM–26-Oct-12
29-5,
A
Figure
P
29-6,
298
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